| 摘要 |
PURPOSE: A delay-locked loop(DLL) by using a digital-to-analog converter controlled by a successive approximation register(SAR) is provided to have an effect of a rapid synchronization time with keeping a good jitter characteristics similar to that of the analog DLL. CONSTITUTION: A delay-locked loop(DLL) by using a digital-to-analog converter controlled by a successive approximation register(SAR)(510) includes a phase detector(500), an SAR(510), a digital-to-analog converter(520), a decoder(530), an up-down counter(540) and a delay line(550). And, the DLL further includes a regulator(560), a direct voltage generator(570), a frequency divider(580), a multiplexor(590), a de-multiplexor(600), a replica circuit(610) and a control circuit(620). In the DLL, the phase detector(500) compares a phase of a feed back clock(fbclk) feedback by an inner clock(Inclk) generated at the delay line(550) through the replica circuit(610) with the phase of the external clock(Extclk) and generates a digital code word by operating the SAR(510) with inputting the detection signal obtained from the comparison result to the SAR(510) during the initial synchronization process.
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