| 摘要 |
PROBLEM TO BE SOLVED: To provide an encoder capable of suitably attaining compatibility between the reduction in an arithmetic load imposed on encoding and the suppression of the circuit scale. SOLUTION: A control unit 20 instructs the encoder 100 as to whether or not the encoder 100 writes data such as ID (identification code) data, IED (ID error detection code) data, CPM (copyright management code) data, zero padding data for each sector to a DRAM 16. A control circuit 170 properly controls changeover circuits 160, 162, 164, 166 in response to the instruction to supply the data whose writing is instructed to a DRAM access circuit 110. The DRAM access circuit 110 uses write address data WA generated by an address generating circuit 180 and an adder circuit 182 to access the DRAM 10 and to write the supplied data to the DRAM 10. COPYRIGHT: (C)2003,JPO
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