发明名称 FRAME SYNCHRONIZING CIRCUIT, PHASE ERROR CUMULATIVE VALUE DETECTOR, AND DIVERSITY CIRCUIT, AND RECEIVER USING THEM
摘要 <p><P>PROBLEM TO BE SOLVED: To obtain satisfactory receiving characteristics by solving the problem of level fluctuation or phase rotation caused by phasing in a digital mobile communication system. <P>SOLUTION: In selecting processing of a branch in the diversity circuit of the receiver, frame synchronism judgment result notice signals 125 and 225 from frame synchronizing parts 118 and 218 of each of branches are investigated and when the frame synchronism judgment results of all the branches show out-of-frame synchronism, the selection of the branch selected up to the moment is maintained and when there is one branch reporting that the frame synchronism judgment result is frame synchronism establishment, selecting processing is performed to select such a branch. By configuring such a diversity circuit, the receiving quality can be improved by the diversity circuit in simple configuration. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003209498(A) 申请公布日期 2003.07.25
申请号 JP20020006909 申请日期 2002.01.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWAI KEIJI;YAMAMOTO HIROMICHI;KUNIEDA MASANORI
分类号 H04L7/00;H04B7/08;H04B7/26;(IPC1-7):H04B7/08 主分类号 H04L7/00
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