发明名称 |
Computer aided design system and computer-readable medium storing a program for designing clock gated logic circuits and gated clock circuit |
摘要 |
A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.
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申请公布号 |
US2003140318(A1) |
申请公布日期 |
2003.07.24 |
申请号 |
US20030376327 |
申请日期 |
2003.03.03 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KITAHARA TAKESHI;ISHIKAWA TAKASHI;USAMI KIMIYOSHI |
分类号 |
G06F1/10;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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