| 摘要 |
<p>A clock generating circuit for generating a clock synchronous with a reference signal. A phase jump of the generated clock is prevented when the reference signal is changed over so as to feed a stable clock, no steady phase error between the reference signal and the generated clock is produced to dispense with phase adjustment and to realize an integrated clock generating circuit. PLL circuits (2) are provided for respective reference signals (1). A clock generating circuit is constituted of the PLL circuits so that one of the outputs of the PLL circuits (2) is selected and inputted into the succeeding-stage PLL circuit (5). Since the variation of the phase of the signal inputted into the PLL circuit (5) of when the reference signal (1) is changed over is reduced, the phase jump of the generated clock (6) is prevented. Therefore the loop gain of the PLL circuits (2, 5) can be increased. No phase error between the reference (1) and the generated clock (6) is produced to dispense with adjustment, and the clock generating circuit can be made an integrated circuit.</p> |
