发明名称 Pulse generation circuit and semiconductor tester that uses the pulse generation circuit
摘要 The present invention provides a pulse generation circuit comprising: a pulse formation circuit for generating normal and dummy pulses according to second delay value data; a data calculation circuit for calculating first delay value data being shown a timing at which the pulses is generated from the pulse formation circuit according to pattern data that has information for determining whether to generate pulses from the pulse formation circuit; a dummy pulse control circuit for controlling generation of a dummy pulse in a no-pulse-generation cycle from the pulse formation circuit according to the second delay value data obtained by detecting said no-pulse-generation cycle from said first delay value data; and a logical gate circuit for eliminating the dummy pulses generated from the pulse formation circuit, being disposed between said pulse formation circuit. solves the problem by providing the delay circuit with a dummy pulse generating means for generating dummy pulses in a cycle in which no pulse is generated usually. Thus, according to the present invention, the power consumption per unit time can be controlled fixedly.
申请公布号 US2003140286(A1) 申请公布日期 2003.07.24
申请号 US20030345230 申请日期 2003.01.16
申请人 SHINBO KENICHI;OONISHI FUJIO;ORIHASHI RITSUROU;FUKUZAKI MASASHI;MOTOKI NOBUO 发明人 SHINBO KENICHI;OONISHI FUJIO;ORIHASHI RITSUROU;FUKUZAKI MASASHI;MOTOKI NOBUO
分类号 G01R31/319;H03K5/135;(IPC1-7):G06K5/04 主分类号 G01R31/319
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