发明名称 |
Semiconductor input/output circuit arrangement |
摘要 |
A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.
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申请公布号 |
US2003137861(A1) |
申请公布日期 |
2003.07.24 |
申请号 |
US20020229337 |
申请日期 |
2002.08.26 |
申请人 |
STMICROELECTRONICS LIMITED |
发明人 |
THIES WILLIAM;FROIDEVAUX NICOLAS |
分类号 |
H01L23/528;H01L27/02;(IPC1-7):G11C5/06 |
主分类号 |
H01L23/528 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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