摘要 |
<p>A phase synchronization circuit (40) for extracting a clock signal CK from a data signal D of random NRZ format and more specifically, a phase synchronization circuit (40) of double loop configuration including a phase comparison circuit (81) and a frequency comparison circuit (10). The phase synchronization circuit (40) can realize both of a wide capture range and high-quality clock signal extraction without requiring a reference clock signal. A clock signal Ca, another clock signal Cb having a phase delayed approximately by 1/4 as compared to the clock signal Ca, and a data signal D are input to a frequency comparison circuit (10) so as to output a logic value according to the magnitude relation between the frequencies of the aforementioned clock signals and the bit rate of the data signal D. Negative feedback of this logic value is performed by a frequency comparison loop F2. Thus, without requiring a reference clock signal, the frequency of the clock signal CK can be approximated to the bit rate of the data signal D and it is possible to realize a wide capture range and extraction of a high-quality clock signal.</p> |