发明名称 RTL power analysis using gate-level cell power models
摘要 A system for analyzing the power consumption of a behavior description of an electrical design includes a structural element library including a set of technology-independent structural macro elements, a macro power model module providing macro power models for one or more of the structural macro elements in the structural element library, and a power estimation module providing a power consumption value of the electrical design using a netlist of interconnected components representative of the electrical design, and the macro power models. The macro power models are associated with corresponding power models in a user-specified gate-level power model library. The power analysis system enables behavior level or RTL power analysis using a user-specified gate-level cell power model library containing arc-based or pin-based power model descriptions or both.
申请公布号 US6598209(B1) 申请公布日期 2003.07.22
申请号 US20010798016 申请日期 2001.02.28
申请人 SEQUENCE DESIGN, INC. 发明人 SOKOLOV SERGUEI A.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址
您可能感兴趣的专利