Dynamic predecoder circuitry for memory circuits

摘要

A predecoder circuit for use in association with a memory circuit is shown to have a dynamic NAND gate formed by series-coupled transistors controlled by a bank active select signal and a row address selection signal. The predecoder circuit also includes a precharge circuit coupled to the dynamic NAND gate and controlled by a precharge signal. The predecoder circuit further includes a first inverter having an input terminal electrically coupled to the dynamic NAND gate and an output terminal selectively electrically connectable to at least one row decoder circuit for the memory circuit. The predecoder circuit finally includes a second inverter arranged in feedback with the first inverter to form a latch.