| 摘要 |
An improved synchronous semiconductor memory device is described in which it is possible to reduce the noise level without compromising the reading speed. The synchronous semiconductor memory device is composed of a memory cell array including a plurality of memory cells for storing data items; a row selection circuit for receiving a row address signal decoded by a row decoder and selecting one row of the memory cell array; a column selection circuit for receiving a column address signal decoded by a column decoder and selecting a plurality of columns of the memory cell array at the same time; a plurality of sense amplifiers for amplifying a plurality of data items which are selected by the row selection circuit and the column selection circuit and are outputted to a plurality of data lines; and a selector element for sequentially outputting the data items which are amplified by the plurality of amplifiers in a time-interleaved manner. Particularly, the plurality of the amplifiers are activated one after another.
|
