| 摘要 |
PROBLEM TO BE SOLVED: To provide a method of operating a memory device so as to read and write data at a high speed using a bus of a small band width. SOLUTION: To the bus connected with memory devices (slave devices) such as DRAM, SRAM, and ROM, master devices (CPU, direct memory access (DMA), etc.), are connected. The bus includes a plurality (number smaller than number of bits within one address) of bus lines to transmit almost all of necessary address, data, and control information to the memory device. The master device transmits a control signal, and the slave device responds to the control signal. To start bus transfer to the bus, the master device delivers a request packet (Fig. 4) of a series of continuous bites including the addresses and control information. The request packet is received in synchronization with an outside clock. The control information includes block size information specifying the amount of data to be inputted (or outputted). COPYRIGHT: (C)2003,JPO |
