| 摘要 |
PROBLEM TO BE SOLVED: To provide a scan test circuit in which the number of test pins required for a scan test of an LSI is reduced to a minimum and which reduces the testing time. SOLUTION: The scan test circuit is provided with a shift register 11 and a shift register 12 which constitute two scan chains, to which a scan-in signal IN1, a scan clock CLK and a scan enable signal EN are supplied and which output a scan-out signal OUT1 and a scan-out signal OUT2, an inverter 2 which inverts the clock CLK and which outputs an inversed clock BCK, a selector 3 which responds to the supply of the enable signal EN, and selects one from among the clock CLK and the inversed clock BCK and which outputs a selected clock CKS so as to be supplied to the shift register 12, and a selector 41 which is synchronized with the clock CLK and which selects one from among the scan-out signals OUT1, OUT2 at the shift registers 11, 12 so as to be output as a scan-out signal SCO1. COPYRIGHT: (C)2003,JPO
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