| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a digital delay line in which jitter characteristics are improved and the area for the delay line can be reduced by one-half in comparison to the existing digital delay line. <P>SOLUTION: The digital delay line is provided with a first NAND gate ND200a to input a first clock signal clk and a first control signal Se1200, a second NAND gate ND200b to input the output signal of the first NAND gate ND200a and a signal Vcc of a high level, a first inverter IV199 to input a second control signal Sel199, a first NOR gate NR199a to input a second clock signal clkb having the phase difference of 180°from the first clock signal clk and the output signal of the first inverter INV199, and a second NOR gate NR199b to input the output signal of the second NAND gate ND200b and the output signal of the first NOR gate NR199b. <P>COPYRIGHT: (C)2003,JPO</p> |
