发明名称 Integrated circuit package and method of manufacture
摘要 An integrated circuit package and a method of manufacturing the package. A silicon chip is attached to the surface of a substrate or attached to the bottom surface of a cavity in the substrate so that the active surface of the chip is exposed. One or more build-up circuit structures are formed over the substrate. Each build-up circuit structure has at least one insulation layer, at least one patterned circuit layer and a plurality of via openings with conductive material therein so that bonding pads on the active surface of the chip connect electrically with the patterned circuit layer through the vias. To form a ball grid array package, solder balls may also be attached to the solder ball pads on the patterned circuit layer so that the bonding pads on the chip are electrically connected to an external circuit through the build-up circuit structure and the solder balls.
申请公布号 US2003133274(A1) 申请公布日期 2003.07.17
申请号 US20020063793 申请日期 2002.05.14
申请人 CHEN KUO-TSO;KUNG CHEN-YUEH 发明人 CHEN KUO-TSO;KUNG CHEN-YUEH
分类号 H01L21/60;H01L23/498;H01L23/538;(IPC1-7):H05K3/30;H01L23/522 主分类号 H01L21/60
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