发明名称 |
Parallel processing logic circuit for sensor signal processing |
摘要 |
A parallel processing logic circuit for sensor signal processing includes sensors and processing units. The sensor and the processing unit are integrated in the same pixel and arranged in a matrix. The processing unit contains a logic structure that consists of a register and a combinational logic function to execute pixel-parallel processing, based on binary data for a sensor, other processing units, and itself. The combinational logic function performs only a predetermined logic function and its dual one exclusively, thereby sharing the circuit resource and reducing the size of the processing unit. The register focusing on compactness also contributes to the small unit.
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申请公布号 |
US2003133621(A1) |
申请公布日期 |
2003.07.17 |
申请号 |
US20020208527 |
申请日期 |
2002.07.29 |
申请人 |
FUJII KOJI;SHIGEMATSU SATOSHI;MORIMURA HIROKI;NAKANISHI MAMORU |
发明人 |
FUJII KOJI;SHIGEMATSU SATOSHI;MORIMURA HIROKI;NAKANISHI MAMORU |
分类号 |
G06F15/80;(IPC1-7):G06K9/42;G06K9/44 |
主分类号 |
G06F15/80 |
代理机构 |
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