| 发明名称 |
Sigma-delta modulator converting digital signals, includes delay circuit producing time difference between output- and input signals. |
| 摘要 |
The sigma-delta converter has a delay circuit (Z) producing a time difference between the output signal y(k) and the digital input signal x(k).
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| 申请公布号 |
DE10162565(A1) |
申请公布日期 |
2003.07.17 |
| 申请号 |
DE20011062565 |
申请日期 |
2001.12.19 |
| 申请人 |
SIEMENS AG |
发明人 |
JELONNEK, BJOERN |
| 分类号 |
H03M3/00;H03M7/00;H03M7/36;(IPC1-7):H03M3/02 |
主分类号 |
H03M3/00 |
| 代理机构 |
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