| 摘要 |
A data transmission system comprising a packet switch module interconnecting LAN adapters, a plurality of input and output ports connected to the LAN adapters such that each pair of input and output ports defines a crosspoint within the switch module, and a memory block located at each crosspoint of the switch module for storing at least one data packet. At each clock time, a scheduler causes a data packet stored in a memory block, among all memory blocks corresponding to a given output port, to be transferred to that output port. The system further comprises a configuration interface mechanism for sending configuration data to the memory control means of memory blocks located at pre-determined crosspoints such that a packet received by corresponding input ports from an input adapter having a speed n times faster than an input adapter transmitting to a single input port is transferred to corresponding output ports at a speed which is n times the transfer speed between a single input port and a single output port.
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