发明名称 |
Method and circuit for adjusting the timing of output data based on the current and future states of the output data |
摘要 |
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.
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申请公布号 |
US2003133527(A1) |
申请公布日期 |
2003.07.17 |
申请号 |
US20020051483 |
申请日期 |
2002.01.17 |
申请人 |
JOO YANGSUNG;BLODGETT GREG A. |
发明人 |
JOO YANGSUNG;BLODGETT GREG A. |
分类号 |
G11C7/10;H03L7/00;H04L7/00;(IPC1-7):H04L7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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