TIMING CONTROL IN DATA RECEIVERS AND TRANSMITTERS

摘要

A Gigabit transceiver (1) has a receiver (2) and a transmitter (3). There is an ADC (5) in the receiver (2) for each channel (A, B, C, D). The ADCs (5) oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs (2) operate off half of the oversampling rate. In the receiver (2) fractionally spaced equalisers (FSEs, 6) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.