| 摘要 |
A microprocessor, including a plurality of registers and an instruction execution module which is adapted to process a sequence of conditional tests. The module uses an instruction set that has the following instructions: A test-and-condition instruction which evaluates each of the conditional tests as true or false and responsive thereto sets respective values in the registers. A priority-test-branch instruction, which causes the instruction execution module, responsive to one of the conditional tests evaluating as true and to the respective values in the registers, to execute a priority code module. A combination-test-branch instruction, which causes the instruction execution module, responsive to evaluations of the conditional tests and to the respective values in the registers, to execute a combination code module.
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