发明名称 Integrated comparator circuit producing complementary binary output potentials includes third bistable flip-flop connecting supply lines selectively
摘要 A third bistable flip-flop (30) connects one (P or N) of the two lines (P, N) with the first supply potential (vdd), in correspondence with the potential difference generated during the third time interval (phase 2).
申请公布号 DE10162277(A1) 申请公布日期 2003.07.17
申请号 DE20011062277 申请日期 2001.12.19
申请人 XIGNAL TECHNOLOGIES AG 发明人 ROGER, FREDERIC
分类号 H03K3/356;(IPC1-7):H03K5/24 主分类号 H03K3/356
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