发明名称 Semiconductor memory device
摘要 When a test mode signal from a control circuit is activated, an operation of a column related circuit is controlled to continuously apply a voltage stress to complementary internal data lines included in the column related circuit. Specifically, a write driver driving a data line is forcedly kept in an inactive state, a sense amplifier is connected to the internal data lines, a column select operation is prohibited and the internal data lines are forcedly, continuously driven in accordance with the write driver, or a voltage setting circuit is connected to the internal data lines and the voltage stress of the internal data lines is accelerated in accordance with the voltage setting circuit during a test. It is possible to continuously apply the voltage stress between complementary data lines of the internal data lines without the need to repeatedly carry out a data write operation, and it is possible to reduce time required for an inter-complementary data line voltage stress test.
申请公布号 US2003133350(A1) 申请公布日期 2003.07.17
申请号 US20020247324 申请日期 2002.09.20
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 NAKAO HIROYUKI
分类号 G01R31/30;G01R31/28;G11C11/401;G11C29/06;G11C29/12;G11C29/14;(IPC1-7):G11C8/00 主分类号 G01R31/30
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