METHOD FOR FORMING BIT LINE OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for forming a bit line of a semiconductor device is provided to remove a concentration of stress at an STI(Shallow Trench Isolation) corner or an edge of a gate by performing a furnace annealing process after a rapid thermal annealing process. CONSTITUTION: An insulating layer having a cell transistor and a bit line contact hole is formed on a substrate. A natural oxide layer and impurities are removed from a lower portion of a contact hole. A bit line is formed by depositing a bit line barrier metal and a bit line metal layer and patterning selectively the bit line barrier metal and the bit line metal layer. A capacitor has a structure of a lower electrode/dielectric layer/upper electrode. One electrode of the cell transistor is connected to the one electrode of the cell transistor. A capacitor upper electrode is activated by a rapid thermal annealing process.