| 摘要 |
A system for reducing the recovery time for the second read in the double-bit cell of a semiconductor memory device. For reading the second bit of the double-bit cell, in addition to swapping the source and drain terminals of a core cell, the source and drain terminals of corresponding double-bit reference cells are also swapped. The system includes a circuit that effects the swapping by providing a path to enable reading the cells in the reverse direction for the second bit read. The swapping enables the bits of the core cell to be accurately determined over the life of the device while at the same time reducing the recovery time needed for execution of the read of the second bit of the double-bit cell.
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