| 摘要 |
A Fiber Channel host bus adapter has a low power, high speed serial to parallel data converter for converting asynchronous serial data into clock aligned, framed, parallel data utilizing a serial in, parallel out register for receiving asynchronous serial data and for providing unframed parallel data. An array of parallel in, parallel out registers is configured to receive parallel data from the serial in, parallel out data register and move the data in a parallel fashion between the parallel in, parallel out registers thereof. A pattern detection circuit identifies a location of a delimiter character within the array of a parallel in, parallel out registers. A selection circuit reads desired data bits from the array of parallel in, parallel out registers in a parallel fashion, based upon the location of the delimiter character, to define a framed parallel output word. A data alignment circuit aligns the framed parallel output word with respect to a clock to define a clock aligned, framed parallel output word.
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