Full digital phase locked loop and circuitry for utilizing the same

摘要

A full digital phase locked loop includes a first counter for continuously counting pulses of a first clock pulse stream to produce a varying count number. A second counter counts pulses of a second clock pulse stream to produce a reference signal when a predetermined number of the pulses is counted. The augend input terminals of an adder receive the varying count number of the first. A comparison signal which appears at one of the adder's output terminals is applied to an exclusive-OR gate for detecting an interval between it and the reference signal. A resettable counter counts pulses of the second pulse stream during the detected interval and produces a count number at periodic intervals. Successively produced count numbers are differentiated and the differentiated count number is supplied to the addend input terminals of the adder as a frequency difference feedback signal.