| 摘要 |
The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers (210 and 216) having similar etching characteristics. Additionally, a hard mask layer (218) and an etch stop layer (214) having similar etching characteristics are used in these structures. In additional embodiments, manufacturing systems (610) are provided for fabricating IC structures. These systems include a controller (600) for interacting with a plurality of fabrication stations (620, 622, 624, 626, 628, 630 and 632).
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