发明名称 |
Zero detect circuit and method for high frequency integrated circuits |
摘要 |
A zero detect circuit. The zero detect circuit includes a data-driven intermediate precharge device coupled to each of a plurality of data inputs to precharge an internal node in response to a data signal received via the corresponding data input. An output responsive to the data signals and to a first clock signal indicates whether all of the data signals represent logical zero data.
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申请公布号 |
US6593778(B1) |
申请公布日期 |
2003.07.15 |
申请号 |
US20000655275 |
申请日期 |
2000.09.05 |
申请人 |
INTEL CORPORATION |
发明人 |
BHARATHI SANDEEP G. |
分类号 |
G06F7/48;H03K19/096;(IPC1-7):H03K19/082;H03K19/20 |
主分类号 |
G06F7/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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