| 摘要 |
A phase-locked loop (PLL) having a digitally controlled oscillator (DCO), where the DCO receives a digital control signal generated by the PLL and an externally generated oscillator clock signal and generates an output signal having a frequency greater than that of the oscillator clock signal. In one embodiment, the DCO is an analog PLL, such as a fractional-N frequency synthesizer, that receives a two-part digital control signal corresponding to the integer and fractional portions of a desired multiplier. The feedback path within the DCO has a dual-modulus divider that is controlled by a modulus controller to apply, over time, an effective divisor value that achieves the desired degree of multiplication. PLLs of the present invention are especially applicable to low-bandwidth, low-noise applications, such as high-multiplication frequency synthesizers and clock filtering, that are integrated into digital ASICs.
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