发明名称 |
MIS semiconductor device having an elevated source/drain structure |
摘要 |
In the first aspect of the invention, a semiconductor device can effectively suppress the adverse short channel effect and the possible occurrence of junction leak current and has a low resistance diffusion layer to realize a short propagation delay time as a plurality of side wall films 4, 5 are formed at least in a part of the area between the gate electrode 3 and an elevated region 8 by laying a plurality of films in an appropriate order.
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申请公布号 |
US6593618(B2) |
申请公布日期 |
2003.07.15 |
申请号 |
US20010994606 |
申请日期 |
2001.11.28 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KAMATA YOSHIKI;NISHIYAMA AKIRA |
分类号 |
H01L21/336;H01L21/8238;H01L29/417;H01L29/49;H01L29/78;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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