| 摘要 |
A self refresh timing generator detects the presence/absence of a read signal output by a control signal generator employed in a DRAM controller to a memory bank and, if no read signal is detected in a predetermined period of time, a refresh signal is generated and output to a refresh suppression register, which has been set in on or off status by the control signal generator in advance. If the refresh suppression register has been set in on status, the refresh signal is blocked and thus not output to the memory bank in the DRAM. If the refresh suppression register has been set in set in off status, on the other hand, the refresh suppression register passes on the refresh signal to the predetermined page of the memory bank associated with the refresh suppression register. As a result, the power consumption of the DRAM is reduced and a high speed read operation can be implemented with a high degree of probability.
|
