发明名称
摘要 PURPOSE:To accelerate the operation of the entire burrel shifter by selecting and outputting a sign bit by a sign look-ahead circuit in the case of performing left arithmetic shift to the data of an N/2 bit width. CONSTITUTION:In half width data shift, the data 10-131 of 32 bits are inputted to an input butter 47, amplified and then simultaneously supplied to the sign look-ahead circuit 46 and a 7-bit shifter 48. To the sign look-ahead circuit 46, shift amount control signals SA0-SA4 and shift type control signals are inputted. When the shift type is the left arithmetic shift, the one to be a most significant bit on a low-order side after the shift is selected from the input data 10-131 as the sign bit and the value of the sign bit is outputted to a sign expansion line 51. In parallel to the operation in the sign look-ahead circuit 46, the input data 10-163 are inputted to the 7-bit shifter 48. The 7-bit shifter 48 is driven and operated by a 7-bit shifter control circuit 45 and the data S0-S63 are outputted.
申请公布号 JP3425205(B2) 申请公布日期 2003.07.14
申请号 JP19940004589 申请日期 1994.01.20
申请人 发明人
分类号 G06F7/00;G06F7/76 主分类号 G06F7/00
代理机构 代理人
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