发明名称
摘要 <p>PROBLEM TO BE SOLVED: To provide a method of manufacturing a chip-size packaged semiconductor device with reduced deformations of a wafer, subsequent to the resin- sealing of the wafer and can easily recognize individual integrated circuits at the cutting of the circuits. SOLUTION: Boundary grooves 7, corresponding to the boundary lines between integrated circuits 2, are formed at the backside of a semiconductor wafer 1 using a blade 17 for cutting. Then, the wafer 1 which has via posts 4 formed on the surface thereof and the grooves 7 formed at the backside thereof, is placed on a bottom force 11, an epoxy resin 5 is fed on the wafer 1 to pressingly contact a top force 12A to the resin 5, and the resin 5 is heated. Since protruding parts 12a are provided at positions which correspond to the boundary lines between the circuits 2 on the surface of the top force 12A, a resin-sealed surface having section grooves 8 for integrated circuit section is formed on the surface of the wafer 1. Thereby, warpage of the wafer 1 due to the difference between the thermal expansion coefficients of the wafer 1 and the resin 5 is relaxed, the deformation of the wafer 1 is reduced, and the boundaries between the circuits 2 become clear.</p>
申请公布号 JP3425378(B2) 申请公布日期 2003.07.14
申请号 JP19980299240 申请日期 1998.10.21
申请人 发明人
分类号 H01L21/301;H01L21/56;H01L23/28;(IPC1-7):H01L21/301 主分类号 H01L21/301
代理机构 代理人
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