发明名称 MASK LAYER AND DOUBLE DAMASCENE INTERCONNECTING STRUCTURE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method for forming an interconnecting structure capable of preventing a size of a via from being reduced even when a trench is misaligned. SOLUTION: A mask layer 57 having four mask films is used. The first mask film 58 and the third mask film 60 have virtually equal etching rates. The second mask film 59 and the fourth mask film 61 have virtually equal etching rates, which are different from those of the first and the third mask films. The via is etched in the first mask film. Then etching of the trench is performed on the third mask film of the mask layer. The via and the trench are then etched in a dielectric material. The second, the third and the fourth mask films are removed while the first mask film remains as a passivation layer for the dielectric material. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003197738(A) 申请公布日期 2003.07.11
申请号 JP20020337918 申请日期 2002.11.21
申请人 AGERE SYSTEMS INC 发明人 HUANG ROBERT Y S;JESSEN SCOTT;KARTHIKEYAN SUBRAMANIAN;LI JOSHUA JIA;OLADEJI ISAIAH O;STEINER KURT G;TAYLOR JOSEPH ASHLEY
分类号 H01L21/28;H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/28
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