发明名称 PRODUCT SUM ARITHMETIC OPERATION UNIT AND PRODUCT SUM ARITHMETIC OPERATION METHOD
摘要 PROBLEM TO BE SOLVED: To realize an arithmetic operation unit having sufficient arithmetic operation accuracy on a floating point number product sum arithmetic operation by an addition of a few circuit scale. SOLUTION: For performing a product sum arithmetic operation for adding third data to the product of first data and second data, the first data and the second data are multiplied by a floating point multiplier 114, and a binary digit string for expressing a mantissa part in a multiplication result is divided into a string for expressing a superordinate digit in the mantissa part and a string for expressing a subordinate digit in the mantissa part. A floating point adder 113 is allowed to first perform addition of third data and subordinate multiplication result data 114L with the binary digit string for expressing the subordinate digit as the mantissa part, and a floating point adder 113 is allowed to thereafter perform addition of an addition result and superordinate multiplication result data 114H with the binary digit string for expressing the superordinate digit as the mantissa part, and rounding processing is applied to the addition result thereafter, and is used as a result of the product sum arithmetic operation. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003196079(A) 申请公布日期 2003.07.11
申请号 JP20010398851 申请日期 2001.12.28
申请人 FUJITSU LTD 发明人 KAWADA SHIRO
分类号 G06F7/485;G06F7/38;G06F7/483;G06F7/499;G06F7/50;G06F7/544;G06F17/10;(IPC1-7):G06F7/50 主分类号 G06F7/485
代理机构 代理人
主权项
地址