| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a system clock generating circuit that causes no discontinuity to a frequency of a system clock even when signal interruption takes place in a reference synchronizing signal and a synchronizing signal of a video signal is selected. <P>SOLUTION: A selection circuit 16 selects a frequency division output signal S202 generated from the reference synchronizing signal when a signal detection circuit 15 detects a reference synchronizing signal or selects a frequency division output signal S102 generated from the video signal when the circuit 15 detects signal interruption of the reference synchronizing signal. A phase comparator circuit 19 compares a phase of the frequency division output signal S30 selected by the selection circuit 16 with a phase of a frequency division output signal S401 from a voltage controlled crystal oscillator (VCXO) 17 and controls the oscillation frequency from the voltage controlled crystal oscillator (VCXO) 17 so that the phase difference becomes zero. A frequency division control circuit 20 gives a reset pulse to a corresponding frequency divider circuit so that a frequency division output signal not selected by the selection circuit 16 is synchronized with the frequency division output signal S401 to control a frequency division operation timing. <P>COPYRIGHT: (C)2003,JPO |
