| 摘要 |
<P>PROBLEM TO BE SOLVED: To generate a frequency-multiplied clock directly from a multiphase clock. <P>SOLUTION: In a circuit block BL1 of a multiphase-clock processing circuit used for a clock-frequency multiplying circuit, the series circuit comprising PMOS transistors P1, P1' is provided connectively between a high-level potential HL and an output terminal U1. Similarly, the series circuit comprising NMOS transistors N1, N1' is provided connectively between a low-level potential LL and the output terminal U1. Further, to the respective gates of the PMOS transistors P1, P1', an inverted signal Ck1B of a clock signal Ck1 is inputted directly and via an inverter IV1. Similarly, to the respective gates of the NMOS transistors N1, N1', a clock signal Ck2 is inputted directly and via an inverter IV2. <P>COPYRIGHT: (C)2003,JPO |
