发明名称 MULTIPLIER
摘要 PROBLEM TO BE SOLVED: To solve problems that the circuit scale gets large and that electric power consumption increases, because a complicated correction circuit is required to be added in an output part or the like to compensate fluctuation of a bias voltage or the like, in a conventional multiplier using an MOS transistor. SOLUTION: This multiplier has NMOS transistors 3, 4, 5, and constant- voltage sources 6, 9, 12 connected respectively to gates of the NMOS transistors 3, 4, 5. In the multiplier, a voltage value in the constant-voltage source 9 is made equal to a voltage value in the constant-voltage source 12, and the NMOS transistor 4 and the NMOS transistor 5 are formed to be mutually the same. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003196578(A) 申请公布日期 2003.07.11
申请号 JP20010391355 申请日期 2001.12.25
申请人 SONY CORP 发明人 HIRABAYASHI ATSUSHI;KOMORI KENJI
分类号 G06G7/12;G06G7/16;G06G7/163;G06G7/164;H03F3/45;(IPC1-7):G06G7/12 主分类号 G06G7/12
代理机构 代理人
主权项
地址