发明名称 A/D CONVERTER AND SIGNAL PROCESSING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide an A/D converter in which a temporal margin can be provided between A/D conversions without increasing the burden on a CPU or occupying a bus. SOLUTION: The A/D converter 32 comprises an A/D converter 34 performing A/D conversion, a timer 35 performing count operation and outputting a count end signal when a specified count is reached, and an A/D conversion control circuit 33 receiving the count end signal from the timer 35 and delivering an A/D conversion start command to the A/D converter 34. The A/D converter 32 has a function for making a decision whether A/D conversions to be performed are left or not upon ending A/D conversion by the A/D converter 34 and restarting count operation of the timer 35 if A/D conversions to be performed are left. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003198369(A) 申请公布日期 2003.07.11
申请号 JP20010395835 申请日期 2001.12.27
申请人 FUJITSU TEN LTD 发明人 TANI TAIJI
分类号 H03M1/12;(IPC1-7):H03M1/12 主分类号 H03M1/12
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