发明名称 |
INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To perform the read or write of data by one memory access in a microprocessor or the like having a cache memory or memory even when addresses are not neatly arranged according to the size of the designated data in the read or write of the data. SOLUTION: A first address showing the writing designation of the data or the storage designation of the read data is generated by a first address adder 24. A second address to which the first address is added is generated by a second address adder 34. Either one of the first address and the second address is properly selected by first to seventh selectors 51-57 and supplied to first to seventh memory areas 41-47. The first address is supplied to an eighth memory area 48. COPYRIGHT: (C)2003,JPO
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申请公布号 |
JP2003196156(A) |
申请公布日期 |
2003.07.11 |
申请号 |
JP20010399389 |
申请日期 |
2001.12.28 |
申请人 |
FUJITSU LTD |
发明人 |
OKANO HIROSHI;HAYAKAWA FUMIHIKO |
分类号 |
G06F12/04;G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/04 |
代理机构 |
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