| 摘要 |
PROBLEM TO BE SOLVED: To provide a compact and unsynchronized FIFO which does not use a gray code. SOLUTION: A register section 19 consists of a first FIFO 11 which is operated by a slow speed clock ACLK and a second FIFO 12 which is operated by a high speed clock BCLK. The FIFO 11 is controlled by a first control circuit 21 and the FIFO 12 is controlled by a second control circuit 22. Signals, which are made by synchronizing read enable signals ARREQ from the circuit 21 with the clock BCLK, are outputted to the circuit 22 and data are transferred to the FIFO 12 from the FIFO 11 with the high speed clock. In the input side, the FIFO state is outputted by the circuit 21 which is operated by the clock ACLK and in the output side, the FIFO state is outputted by the circuit 22 which is operated by the clock BCLK. Thus, a FIFO state is surely recognized without using a gray code. COPYRIGHT: (C)2003,JPO
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