发明名称 CLOCK GENERATING METHOD AND CLOCK GENERATOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generating method in which a phase of a generated clock is not shifted even when a reference clock is switched a plurality of times. <P>SOLUTION: A clock generator has a frequency measuring part 17 for measuring the frequency of a reference clock 25 and a frequency control part 28 for matching the clock to be outputted with the frequency of the reference clock and by synchronizing generated clocks 26 with the frequency of the reference clock as a reference, the shift in the phase of the generated clock is eliminated, so that a data slip does not occur. In such a clock generating method, the phase of the generated clock is not shifted even when the reference clock is switched a plurality of times. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003198519(A) 申请公布日期 2003.07.11
申请号 JP20010391455 申请日期 2001.12.25
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FUJIKI KAZUYOSHI
分类号 H04L7/00 主分类号 H04L7/00
代理机构 代理人
主权项
地址