发明名称 DEVICE, METHOD AND PROGRAM FOR VERIFYING LSI DESIGN
摘要 PROBLEM TO BE SOLVED: To optimize interface specifications among modules by verifying properties for every module. SOLUTION: This method for verifying LSI (large scale integration) is characterized by reading circuit description (S11), analyzing signal connection relation among hierarchies analyzed from the highest order hierarchy about the circuit description (S12), storing data of the signal connection relation among the hierarchies in a common data base, reading properties of modules to be verified in the circuit description, extracting only property places in which signals among the modules to be verified are included from the common data base (S13), extracting output operation properties in which an output operations in modules on the output side of the respective signals are defined and expecting operation properties in which expecting operations existing in modules on the input side from the properties (S14) and comparing the output operation properties with the expecting operation properties (S15) in functional verification of an LSI by using logical simulation. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003196342(A) 申请公布日期 2003.07.11
申请号 JP20010398319 申请日期 2001.12.27
申请人 TOSHIBA CORP 发明人 MATSUOKA YOSHIKI;HORIKAWA KAZUNARI;TSUCHIYA TAKEHIKO;YANO EIICHI;NISHIDE TAKEO
分类号 G01R31/28;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G01R31/28
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