发明名称 OPERATING SYSTEM
摘要 PROBLEM TO BE SOLVED: To realize efficient execution of a large scale program comprising a plurality of program modules directly by means of hardware without using a general purpose CPU. SOLUTION: A gate array 43 performs operation by means of hardware according to an FPGA data module stored in an FPGA data memory specified in a shift register 40. When a call detecting section 44 detects that a module stored in the FPGA data memory calls other module, data of intermediate operational results stored in a flip-flop 43b is retreated into a retreat stack 45 and an argument being delivered to a called module is stored temporarily in an argument delivery section 46. When an FPGA data memory storing the called module is specified, subsequently, to the shift register 40 and reset to a calling module, data retreated into the retreat stack 45 is rewritten to the flip-flop 43b. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003198362(A) 申请公布日期 2003.07.11
申请号 JP20010401462 申请日期 2001.12.28
申请人 TOKYO ELECTRON DEVICE LTD;NISHIHARA AKINORI 发明人 MITA TAKASHI;NISHIHARA AKINORI
分类号 G06F9/40;G06F9/00;G06F9/54;G06F12/00;G06F15/78;H03K19/177;(IPC1-7):H03K19/177 主分类号 G06F9/40
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