发明名称 |
METHOD AND PROGRAM PRODUCT FOR MODELING CIRCUITS WITH LATCH BASED DESIGN |
摘要 |
A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch. |
申请公布号 |
WO02052453(A3) |
申请公布日期 |
2003.07.10 |
申请号 |
WO2001CA01731 |
申请日期 |
2001.12.05 |
申请人 |
LOGICVISION, INC.;NADEAU-DOSTIE, BENOIT;MAAMARI, FADI;BUREK, DWAYNE |
发明人 |
NADEAU-DOSTIE, BENOIT;MAAMARI, FADI;BUREK, DWAYNE |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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