| 摘要 |
A memory structure includes decoders for enabling multiple rows to be read in response to a single row address. This memory structure helps to reduce the number of ports that are required for the memory structure and, thus, reduces the die area occupied by the memory structure. The decoding logic may divide a row address into most significant bits and least significant bits that are processed differently for decoding. The memory structure may be especially wall adapted for environments, such as microprocessors, where the space occupied by the memory structure should be optimized. |
