| 摘要 |
The present invention relates to an integrated circuit test method, said method using at least one test vector comprising serialized input (SHIFT_IN) and output values. It is characterized in that it comprises the following steps: setting the circuit in the serialization mode at the start of a clock cycle (CLK), applying serialized input values (SHIFT_IN) of the test vector (V) in parallel to the selectors (S), loading said serialized input values (SHIFT_IN) in parallel into said simple flip-flops (FF) associated with said selectors (S), setting the circuit in the normal mode, capturing serialized result values (SHIFT_RES) in the flip-flops (FF), recovering said serialized result values (SHIFT_RES) in said flip-flops (FF) in parallel and comparing them with the serialized output values (SHIFT_OUT) of the test vector (V).
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