Schaltungsanordnung zur Bereitstellung eines Ausgangssignals mit einstellbarer Flankensteilheit

摘要

The invention relates to a circuit arrangement for the provision of an output signal with adjustable flank pitch, whereby the several, parallel inverter output stages (5, 6; 7, 8; 9, 10; 11, 12) are connected in parallel on the load side. The output stages are controlled with a common trapezoidal signal (C), generated by a ramp signal generator (3). The output transistors (5 to 12) are thus sequentially switched on and off. A precisely adjustable, reduced flank pitch for an output signal with a desired amplifier power can thus be achieved with a low spatial requirement. Furthermore an adjustable reduction in the high-frequency interference emissions from integrated circuits can thus be achieved.