Memory cell with trench transistor has pn junctions defining channel region abutting walls of trench within curved area at base of trench

摘要

The memory cell has a gate electrode (4) contained in trench between a source region (2) and a drain region (3), with separation of the gate electrode from the semiconductor material by a dielectric layer acting as a memory medium. The pn junctions (14) defining the channel region (5) abut the walls of the trench within a curved lower area at the base (7) of the trench.